The present invention relates generally to the design of integrated circuits and, more specifically, to software tools for sizing various elements of an integrated circuit design.
In general, the problem of transistor sizing in an integrated circuit design may be stated as follows: given an initial circuit and floor planning (i.e., geometry) information, generate an improved circuit by changing transistor widths such that the improved circuit meets delay constraints, and minimizes objective functions, e.g., energy dissipation or area. A conventional approach to determining transistor sizes in an unsized asynchronous circuit assumes that every gate has the same delay, i.e., the unit delay model. However, forcing a unit delay model on a circuit may not result in a very good circuit in that some gates are fundamentally more difficult or slower than other gates.
Most commercial sizing tools are intended for synchronous circuit design and are characterized by limitations specific to the synchronous domain which make them virtually unworkable in an asynchronous design flow. For example, most sizing tools measure logic delay from latch to latch, i.e., consequently they generally expect only acyclic circuit paths. As a result, these tools have difficulty dealing with paths that loop back on themselves. They include only ad-hoc techniques to cut loops that often produce inferior paths that are hard to size. This can be an irritating problem for the relatively rare instances of such loops in synchronous circuits, and an overwhelming obstacle for asynchronous designs in which such loops, e.g., handshaking loops, predominate.
In addition, most commercial sizing tools assume that only combinational logic (e.g., NAND gates, inverters, and NOR gates) is used, and thus do not typically support dynamic logic (e.g., domino logic). They are also limited to circuits that are flattened. Thus they are solving an instance-based problem with is not applicable to a hierarchical design. In addition, commercial sizing tools size circuit on the basis of gates, i.e., the pull-up network and pull-down network are sized as one variable, which limits the optimization space. Finally, most commercial sizing tools allow only a small number of primitives that are fixed in size and characterized in advance, thus limiting the available options in creating and solving the optimization problem.
It is therefore desirable to provide tools for use in the design of integrated circuits which address some or all of the aforementioned issues.
According to the present invention, methods and apparatus are provided for facilitating physical synthesis of an integrated circuit design. A set of paths between a set of observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. According to a specific embodiment, a signal transition has two types a downward transition in which the signal transitions from logical 1 to 0, and a upward transition in which the signal transitions from logical 0 to 1. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays meets or exceeds the unit delay. According to various embodiments, an objective function is minimized subject to the delay constraints, the objective function relating to the unit delay and a measure of energy consumption. According to various embodiments, amortization of the delay constraint in this manner is applied to an asynchronous circuit design characterized by an asynchronous handshake protocol. According to some of these embodiment, the asynchronous circuit design is a hierarchical design.
According to another specific embodiment, the netlist includes representations of a plurality of leaf cells each having at least one input port and at least one output port. In this embodiment, at least a portion of the set of paths is generated by traversing each leaf cell from the input to output ports to identify at least one of the paths associated therewith. According to one embodiment, the input and output ports for the leaf cells correspond to a subset of the observable nodes. In a further embodiment, at least a portion of the set of paths is generated by concatenating selected ones of the paths (e.g., by making some ports non-observable).
According to another specific embodiment, path generation results for a first instance of a particular leaf cell type are applied to at least one other instance of the particular leaf cell type.
According to a specific embodiment, the delay of each transition is determined by the size of the transistors in the pull up half operator in the case of a rising transition and a pull down half operator in the case of a falling transition. In this embodiment, the transistors associated with the pull up and pull down half operators for a given node are sized independently. According to a more specific embodiment, each of the individual delays are determined with reference to a delay model for each of the pull up and pull down half operators for each of the gates in each path, and wires between the nodes. According to an even more specific embodiment, the delay model represents each half operator as a resistor, a load on the corresponding node as a capacitor, and a wire connecting the half operator and the load as a wire xcfx80 model. According to yet another specific embodiment, the individual delays are determined with reference to wire length data derived from actual geometry information corresponding to the circuit design.
According to another embodiment, methods and apparatus are provided for facilitating physical synthesis of an integrated circuit design. A set of paths is generated from a netlist representing the circuit design. Each path corresponds to a sequence of nodes each having upward and downward signal transitions associated therewith. For each of selected nodes, the corresponding upward transition is represented by a pull up half operator and the corresponding downward transition is represented by a pull down half operator. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. Transistors associated with the pull up half operator for each selected node are sized independently from transistors associated with the corresponding pull down half operator. According to various embodiments, this method is applied to an asynchronous circuit design characterized by an asynchronous handshake protocol. According to some of these embodiment, the asynchronous circuit design is a hierarchical design.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.